DACs and analog-to-digital converters ("ADCs") have recently come into more widespread use with the development of suitable process technology and the increase in digital audio and other applications. One common type of ADC is the all-parallel, or so-called "flash", converter which provides a relatively fast conversion. DACs are commonly used in flash ADCs to provide reference voltage output taps. Such DACs are described, for example, in Analog-Digital Conversion Handbook, Third Edition, by Analog Devices, Inc.
A typical multi-phase flash ADC is shown in block diagram form in FIG. 1. As shown, the n-bit flash ADC includes an analog input lead 10, a DAC 12, 2.sup.m -1 (where m&lt;n) latched comparators (labeled LC1 through LC2.sup.m -1), a control signal lead 14, and an encoding logic unit 16. An analog input signal is received on analog input lead 10 and provided to each of the 2.sup.m -1 latched comparators. DAC 12 is a so-called "string DAC" and includes 2.sup.n resistors (labeled R1 through R2.sup.n) connected in series between reference voltage V.sub.REF and ground. All nodes between the 2.sup.n resistors are used to provide comparator reference voltages and are connected to the inputs of switch matrix 13. The switch matrix is used to connect a subset of these DAC reference voltages to the latched comparator inputs during each phase of the ADC conversion. The control signal lead 14 is connected to each of the latched comparators and receives the control signal ENCODE COMMAND for controlling operation of the comparators. Each comparator provides an output to encoding logic unit 16 which, in turn, provides an n-bit digital output.
2.sup.n -1 different reference voltages are provided by the string DAC 12 to the switch matrix 13. The switch 13 provides appropriate reference voltages to the 2.sup.m -1 comparators. The reference voltages provided by the string DAC 12 differ between adjacent taps by a voltage level corresponding to one least-significant bit ("LSB") of the digital output code. Each comparator performs a comparison of the analog input signal with the appropriate reference voltage received from switch matrix 13 upon receipt of the ENCODE COMMAND signal; it then provides a binary output signal to encoding logic unit 16. Each comparator that receives a reference voltage which is less than the voltage of The input signal will output a signal corresponding to a logical "one" and each comparator that receives a reference voltage which is greater than that of the input signal will output a signal corresponding to a logical "zero".
The encoding logic unit 16 then converts the thermometer output code of the comparators to an n-bit digital output code. As will be understood by those skilled in the art, the digital output signal may be in different formats such as binary, Gray code, or other. Another digital output signal is provided along bus 15 to switch control logic unit 17 which provides control signals along line 19 to control operation of the switch matrix 13. Typically, the n-bit digital output signal is produced in multiple phases. Multi-phase flash ADCs are known in which a multi-bit conversion occurs over a number of phases or time intervals. In a multi-phase flash ADC, the digital output signal during a first phase controls the operation of the switches within switch matrix 13 during an immediately subsequent phase. A typical 10-bit flash ADC, for example, operates in three phases in which the four MSBs are generated during phase 1, the next three less-significant bits are generated during phase 2, and the three LSBs are generated during phase 3. Those skilled in the art will appreciate that during each subsequent phase, the string DAC produces a "finer" set of reference voltages (i.e., the reference voltages of a subsequent phase are closer in value to the input signal than those of a previous phase) for comparison to the analog input signal.
During a first phase, the string DAC provides a first set of "coarse" reference voltages to the comparators for comparison with the analog input signal. A set of the most-significant bits (MSB) of the digital output code is generated during the first phase. During the second and immediate subsequent phase, the digital output code generated during the first phase controls the switches within the switch matrix 13 for providing a finer set of reference voltages to the comparators. During this second phase, a set of less-significant bits (i.e., of lesser significance, bit-wise, than the MSBs generated during the first phase) is generated. The digital output code from the second phase, in turn, controls the switches within the switch matrix 13 during the third phase and an even finer set of reference voltages is provided to the comparators for generation of the LSBs of the output code.
Ideally, the string DAC should produce an analog output signal which linearly increases as the digital input code increases. However, as will be readily appreciated by those skilled in the art, the analog output signal of most DACs tend to be non-linear. INL error is the maximum deviation at any point in the transfer function (a graph of the analog output signal verses the digital input code) of the output voltage level from its ideal level. INL errors of a string DAC used in a flash ADC may affect the accuracy of the ADC output.
INL errors in string DACs can be caused by gradients in the resistance values of the resistors within the string DAC. The gradients are typically caused by process inaccuracies (i.e., mismatches in sheet resistance values which occur during fabrication). While string DACs typically include a large number of resistors which ideally have the same resistance value, process gradients result in such resistors having different values. The gradients can be linear, non-linear or random and each can cause INL errors.
Accordingly, a general object of the present invention is to provide a string DAC having reduced INL errors due to resistor process gradients.
Other objects and advantages will be apparent from the detailed description below.